LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;


entity programcounter is
  port ( 
    -- clock signal
    CLK							:		in	std_logic;
    nReset      :   in std_logic;
    PCEN        :   in std_logic;
    baseAddr    :   in std_logic_vector(31 downto 0);
    next_in     :   in std_logic_vector (31 downto 0);
    curr_out    :   out std_logic_vector (31 downto 0)
  );
end programcounter;

architecture arch of programcounter is
   signal q, q_n : std_logic_vector (31 downto 0);

begin
  proc : process(CLK,nReset,q, q_n, baseAddr)
  begin
    q <= q;
    if (nReset = '0') then
      q <= baseAddr;
    elsif rising_edge(CLK) then
      q <= q_n;
    end if;
  end process proc;

  q_n <= next_in when PCEN = '1' else
        q when PCEN = '0' else
        x"00000000";

  curr_out <= q;
  
end arch;